1. Field of the Invention
The present invention relates to an insulated-gate field-effect transistor having high-mobility channel and a short gate length, and a method of fabricating the same. Further, the present invention is concerned with a semiconductor device employing the insulated-gate field-effect transistors. The transistor according to the present invention is useful when applied to a semiconductor device for use in an electronic circuit including a logic circuit, an analog circuit, and so on, particularly, in a field where high speed and low power consumption are required.
2. Description of the Related Art
In the case of a silicon semiconductor device, particularly, a field effect transistor, larger scale integration of a circuit has so far been realized and higher performance thereof has been obtained by downsizing the device. However, when the gate of a transistor is e.g., a size less than 50 nm, it has become extremely difficult to achieve high performance through downsizing only. For such a hyperfine device, it has become advantageous to use the so-called SOI (Silicon-on-Insulator) structure wherein a thin silicon layer in an active region is laid on top of an insulator layer, in place of a device which has thus far been in widespread use, wherein a region near the surface of a single crystal silicon substrate is used as an active region thereof.
Among other things, a double-gate structure with a channel layer, sandwiched between gates disposed on opposite-sides thereof, is regarded the most advantageous structure for operation of a hyperfine device. As for the double-gate structure, a structure and a method of fabricating the same are disclosed in, for example, JP-A No. 16255/2002. Another form of the double-gate structure is a structure called the fin-shaped double-gate structure (referred to as a FinFET). An example thereof is shown in, for example, proceedings of International Electronic Device Conference (IEDM), 1988, pp. 1032-1034.
Meanwhile, attention has lately been focused on use of a strained silicon transistor instead of attempting to enhance performance simply through downsizing thereof. The strained silicon transistor is a transistor wherein carrier mobility is enhanced by applying strain to silicon in an attempt to increase performance of the device. As shown in, for example, Nikkei Electronics, issue of Jul. 16, 2001, pp. 63-67, an example thereof is capable of improving its performance on the order of 35% provided that the gate size thereof remains the same. Further, another example of a strained SOI transistor is shown in, for example, JP-A No. 321307/1997. However, with the device shown in JP-A No. 321307/1997, there has been the need for a strain-relaxed silicon germanium layer invariably being in contact with a strained silicon channel in order to maintain strain. Therefore, according to JP-A No. 286418/2000, it has been described that a silicon germanium layer is removed in a stage of fabricating a substrate.
Now, drawbacks of the strained SOI transistor tackled so far will be described. For example, a structure shown in JP-A No. 321307/1997 is that of the conventional, representative strained SOI transistor. With this example, presence of a silicon germanium layer to apply strain is invariably required underneath the strained silicon to serve as a channel. However, in the case of a hyperfine device, it is also necessary to reduce the thickness of the channel layer, corresponding to a miniaturization in gate size, in order to reduce leakage current from the source to the drain, that is, a so-called punch-through current. With the conventional strained SOI, it has been impossible to sufficiently reduce the thickness of the layer upon the insulator layer because of the need for presence of the silicon germanium layer. Further, the silicon germanium layer has lower energy against holes as compared with the strained silicon. Accordingly, there has occurred a problem that a p-type transistor is more susceptible to occurrence of punch-through.
Furthermore, one drawback of substrates employed previously is that they have required a fabrication process using a special method of bonding, among other things, and consequently, fabrication cost thereof becomes higher in comparison with a conventional Si or SOI substrate.